This relates to image sensors, and more particularly, to photodiodes used in an image pixel array of an image sensor and the methods of forming the photodiodes.
Electronic devices such as cellular telephones, cameras, and computers often include imaging systems that include digital image sensors for capturing images. Image sensors may be formed having a two-dimensional array of image pixels containing photodiodes that convert incident photons (light) into electrical signals. Electron-hole pairs may be generated when photons with a sufficient energy are incident on a photodiode region of a pixel.
In pixels of a charge-coupled device (CCD) or CMOS based image sensors, it may be necessary to apply large voltages to a transfer gate that is adjacent to the photodiode region of a pixel to enable a total transfer of charges from the photodiode to the adjacent charge-coupled device or floating diffusion region. Conventional CCD and CMOS image sensors include pixels having a shallow, or thin pinning layer with a peak dopant concentration below an oxide layer that is typically formed over the photodiode region of the pixel.
Forming a thin pinning layer enables reduced smear in image sensors. Because fewer carriers are generated in a thin pinning layer compared to a thicker pinning layer, the risk of lateral charge carrier spread (or carrier diffusion) within the neutral region of the pinning layer to other regions of the pixel where these excess charge carriers (such as electrons in devices using n-type photodiodes) can be interpreted as image signals is reduced, thereby reducing smear. Forming a thin pinning layer can also reduce the depth of an associated photodiode implant required to store a given amount of charge as required by the dynamic range constraints of the imager which uses the photodiode, which reduces the so-called empty diode potential, or pinned potential. Reducing the empty-diode potential reduces the voltage required on the transfer gate to enable a complete readout of charge collected in photodiode into the adjacent CCD or floating diffusion region. For a typical CCD device built with a lateral-overflow drain, (e.g. U.S. Pat. No. 4,717,945), the reduced empty-diode potential also reduces the so-called, electronic shutter voltage, which is the voltage applied to the substrate as required to completely empty the photodiodes.
Current approaches to forming pinning layers involve implanting ion impurities predominantly in a region of the semiconductor substrate above the photodiode layer. Conventional pinning layers associated with a photodiode have a peak impurity ion dopant concentration in the semiconductor substrate in which the photodiode is formed.
In conventional manufacturing, pinning layers are implanted into a semiconductor (e.g., silicon) substrate into bare silicon, or through a dielectric overlayer that is formed over the substrate. Some conventional pinning layers in image pixels are implanted through a dielectric layer of a greater thickness as the dielectric layer formed above a CCD's buried channel implant or floating diffusion implant used to read out the photodiode charge. Conventional methods to form pinning layers also involve forming a gate electrode before implanting a photodiode region in the semiconductor substrate.
Conventional practice in forming the pinning layer for a photodiode aims to ensure that the implant of impurity dopants associated with the pinning layer goes through any dielectric overlayers that are formed over the photodiode and has a peak concentration in the silicon substrate to avoid variability in the device characteristics caused by any thickness variation in the overlayers. Because the tail of the impurity dopant implant profile falls off quickly, conventional practice aims to avoid implanting impurity dopants in the dielectric overlayers, because small changes in thickness of the over-layers can result in significant change in the amount of dopant that gets into the silicon, the conventional location for the pinning layer.
It would be therefore be desirable to provide improved methods for implanting shallow pinning layers for photodiodes used in image pixel arrays.